UART_TX Project Status
Project File: UART_TX.xise Parser Errors: No Errors
Module Name: UART_TX Implementation State: Programming File Generated
Target Device: xc3s400-5pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 20 7,168 1%  
Number of 4 input LUTs 18 7,168 1%  
Number of occupied Slices 25 3,584 1%  
    Number of Slices containing only related logic 25 25 100%  
    Number of Slices containing unrelated logic 0 25 0%  
Total Number of 4 input LUTs 42 7,168 1%  
    Number used as logic 18      
    Number used as a route-thru 24      
Number of bonded IOBs 3 141 2%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 2.17      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentسه شنبه 11. آوريل 18:06:21 201701 Warning (0 new)0
Translation ReportCurrentسه شنبه 11. آوريل 18:06:27 2017000
Map ReportCurrentسه شنبه 11. آوريل 18:06:33 2017002 Infos (0 new)
Place and Route ReportCurrentسه شنبه 11. آوريل 18:06:41 2017002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentسه شنبه 11. آوريل 18:06:45 2017006 Infos (0 new)
Bitgen ReportCurrentسه شنبه 11. آوريل 18:06:51 2017001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentسه شنبه 11. آوريل 18:06:51 2017
WebTalk Log FileCurrentسه شنبه 11. آوريل 18:06:56 2017

Date Generated: 04/11/2017 - 18:08:45