Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s400
Project ID (random number) 453774348f7a49179728285585685d17.0A6F68BE758541CE9093FC54252E463B.34 Target Package: pq208
Registration ID __0_0_0 Target Speed: -5
Date Generated 2017-04-11T18:06:51 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Pentium(R) CPU G645 @ 2.90GHz CPU Speed 2893 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 13-bit adder=1
  • 4-bit adder=1
Counters=2
  • 13-bit up counter=1
  • 4-bit up counter=1
ROMs=1
  • 16x1-bit ROM=1
Registers=3
  • Flip-Flops=3
MiscellaneousStatistics
  • AGG_BONDED_IO=3
  • AGG_IO=3
  • AGG_SLICE=25
  • NUM_4_INPUT_LUT=42
  • NUM_BONDED_IOB=3
  • NUM_BUFGMUX=1
  • NUM_CYMUX=24
  • NUM_LUT_RT=24
  • NUM_SLICEL=25
  • NUM_SLICE_FF=20
  • NUM_XOR=26
NetStatistics
  • NumNets_Active=63
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=12
  • NumNodesOfType_Active_CNTRLPIN=20
  • NumNodesOfType_Active_DOUBLE=67
  • NumNodesOfType_Active_DUMMY=79
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_GLOBAL=9
  • NumNodesOfType_Active_HUNIHEX=3
  • NumNodesOfType_Active_INPUT=93
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=53
  • NumNodesOfType_Active_OUTPUT=58
  • NumNodesOfType_Active_PREBXBY=1
  • NumNodesOfType_Active_VFULLHEX=7
  • NumNodesOfType_Gnd_INPUT=2
  • NumNodesOfType_Gnd_OMUX=2
  • NumNodesOfType_Gnd_OUTPUT=2
  • NumNodesOfType_Gnd_PREBXBY=2
SiteStatistics
  • IOB-DIFFS=2
  • SLICEL-SLICEM=17
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=3
  • IOB_INBUF=2
  • IOB_OUTBUF=1
  • IOB_PAD=3
  • SLICEL=25
  • SLICEL_C1VDD=2
  • SLICEL_CYMUXF=12
  • SLICEL_CYMUXG=12
  • SLICEL_F=22
  • SLICEL_FFX=10
  • SLICEL_FFY=10
  • SLICEL_G=20
  • SLICEL_GNDF=10
  • SLICEL_GNDG=12
  • SLICEL_XORF=14
  • SLICEL_XORG=12
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IOB
  • O1=[O1_INV:0] [O1:1]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:1]
IOB_PAD
  • DRIVEATTRBOX=[12:1]
  • IOATTRBOX=[LVCMOS25:3]
  • SLEW=[SLOW:1]
SLICEL
  • BX=[BX_INV:1] [BX:2]
  • BY=[BY:1] [BY_INV:0]
  • CE=[CE:12] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:12]
  • CLK=[CLK:12] [CLK_INV:0]
  • SR=[SR:7] [SR_INV:1]
SLICEL_CYMUXF
  • 0=[0:12] [0_INV:0]
  • 1=[1_INV:0] [1:12]
SLICEL_CYMUXG
  • 0=[0:12] [0_INV:0]
SLICEL_FFX
  • CE=[CE:10] [CE_INV:0]
  • CK=[CK:10] [CK_INV:0]
  • D=[D:9] [D_INV:1]
  • FFX_INIT_ATTR=[INIT0:9] [INIT1:1]
  • FFX_SR_ATTR=[SRLOW:10]
  • LATCH_OR_FF=[FF:10]
  • SR=[SR:7] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:3] [SYNC:7]
SLICEL_FFY
  • CE=[CE:10] [CE_INV:0]
  • CK=[CK:10] [CK_INV:0]
  • D=[D:10] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:10]
  • FFY_SR_ATTR=[SRLOW:10]
  • LATCH_OR_FF=[FF:10]
  • SR=[SR:6] [SR_INV:1]
  • SYNC_ATTR=[ASYNC:3] [SYNC:7]
SLICEL_XORF
  • 1=[1_INV:0] [1:14]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IOB
  • I=2
  • O1=1
  • PAD=3
IOB_INBUF
  • IN=2
  • OUT=2
IOB_OUTBUF
  • IN=1
  • OUT=1
IOB_PAD
  • PAD=3
SLICEL
  • BX=3
  • BY=1
  • CE=12
  • CIN=12
  • CLK=12
  • COUT=12
  • F1=22
  • F2=8
  • F3=8
  • F4=6
  • G1=20
  • G2=8
  • G3=4
  • G4=2
  • SR=8
  • X=13
  • XQ=10
  • Y=12
  • YQ=10
SLICEL_C1VDD
  • 1=2
SLICEL_CYMUXF
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL_CYMUXG
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL_F
  • A1=22
  • A2=8
  • A3=8
  • A4=6
  • D=22
SLICEL_FFX
  • CE=10
  • CK=10
  • D=10
  • Q=10
  • SR=7
SLICEL_FFY
  • CE=10
  • CK=10
  • D=10
  • Q=10
  • SR=7
SLICEL_G
  • A1=20
  • A2=8
  • A3=4
  • A4=2
  • D=20
SLICEL_GNDF
  • 0=10
SLICEL_GNDG
  • 0=12
SLICEL_XORF
  • 0=14
  • 1=14
  • O=14
SLICEL_XORG
  • 0=12
  • 1=12
  • O=12
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 85 60 0 0 0 0 0
bitgen 265 263 0 0 0 0 0
cse_server 5 0 0 0 0 0 0
map 314 281 0 0 0 0 0
netgen 7 6 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngcbuild 1 1 0 0 0 0 0
ngdbuild 317 315 0 0 0 0 0
obngc 1 1 0 0 0 0 0
par 280 272 8 0 0 0 0
trce 268 268 0 0 0 0 0
xst 882 867 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ise_p_viewing_a_technology_schematic_xst.htm ( 1 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 1 )
/doc/usenglish/isehelp/pp_n_process_generate_programming_file.htm ( 1 ) /doc/usenglish/isehelp/pp_n_process_launch_rtl_viewer.htm ( 1 )
/doc/usenglish/isehelp/pp_n_process_view_technology_schematic.htm ( 1 ) /doc/usenglish/isehelp/rtv_c_overview.htm ( 1 )
/doc/usenglish/isehelp/rtv_db_lut_content.htm ( 2 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2017-04-07T13:05:58 PROP_intWbtProjectID=0A6F68BE758541CE9093FC54252E463B
PROP_intWbtProjectIteration=34 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan3 PROP_DevDevice=xc3s400
PROP_DevFamilyPMName=spartan3 PROP_DevPackage=pq208
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FDE=6 NGDBUILD_NUM_FDRE=14 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=24 NGDBUILD_NUM_LUT2=3
NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=3 NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=7
NGDBUILD_NUM_LUT4_L=1 NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=26
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FDE=6 NGDBUILD_NUM_FDRE=14 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=4 NGDBUILD_NUM_LUT1=24
NGDBUILD_NUM_LUT2=3 NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=3 NGDBUILD_NUM_LUT3_L=1
NGDBUILD_NUM_LUT4=7 NGDBUILD_NUM_LUT4_L=1 NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_OBUF=1
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s400-5-pq208 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5