Project Statistics |
PROPEXT_xilxSynthMaxFanout_virtex2=100000 |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2017-04-07T13:05:58 |
PROP_intWbtProjectID=0A6F68BE758541CE9093FC54252E463B |
PROP_intWbtProjectIteration=34 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_xilxBitgStart_IntDone=true |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
PROP_DevDevice=xc3s400 |
PROP_DevFamilyPMName=spartan3 |
PROP_DevPackage=pq208 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-5 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_VERILOG=1 |