shc Project Status (03/14/2017 - 11:27:54)
Project File: Shematic.xise Parser Errors: No Errors
Module Name: VHDL_MODULE Implementation State: Programming File Not Generated
Target Device: xc3s400-5pq208
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 1 3584 0%
Number of 4 input LUTs 1 7168 0%
Number of bonded IOBs 5 141 3%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentدنشلبم 13. كارس 16:44:18 2017   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Synthesis Simulation Model ReportOut of Dateدنشلبم 13. كارس 15:02:13 2017
WebTalk ReportCurrentسم شلبم 14. كارس 11:27:49 2017
WebTalk Log FileCurrentسم شلبم 14. كارس 11:27:54 2017

Date Generated: 03/14/2017 - 11:27:54