shc Project Status (03/14/2017 - 11:27:54)
Project File: Shematic.xise Parser Errors: No Errors
Module Name: shc Implementation State: Programming File Generated
Target Device: xc3s400-5pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 51 7,168 1%  
Number of 4 input LUTs 28 7,168 1%  
Number of occupied Slices 36 3,584 1%  
    Number of Slices containing only related logic 36 36 100%  
    Number of Slices containing unrelated logic 0 36 0%  
Total Number of 4 input LUTs 63 7,168 1%  
    Number used as logic 28      
    Number used as a route-thru 35      
Number of bonded IOBs 10 141 7%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 2.06      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentسم شلبم 14. كارس 11:26:13 2017001 Info (1 new)
Translation ReportCurrentسم شلبم 14. كارس 11:27:29 2017000
Map ReportCurrentسم شلبم 14. كارس 11:27:33 2017002 Infos (0 new)
Place and Route ReportCurrentسم شلبم 14. كارس 11:27:40 2017002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentسم شلبم 14. كارس 11:27:43 2017006 Infos (0 new)
Bitgen ReportCurrentسم شلبم 14. كارس 11:27:48 2017001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Synthesis Simulation Model ReportOut of Dateدنشلبم 13. كارس 15:02:13 2017
WebTalk ReportCurrentسم شلبم 14. كارس 11:27:49 2017
WebTalk Log FileCurrentسم شلبم 14. كارس 11:27:54 2017

Date Generated: 03/14/2017 - 11:27:54