shc Project Status (03/14/2017 - 11:27:54) | |||
Project File: | Shematic.xise | Parser Errors: | No Errors |
Module Name: | VHDL_MODULE | Implementation State: | Programming File Not Generated |
Target Device: | xc3s400-5pq208 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 1 | 3584 | 0% | |
Number of 4 input LUTs | 1 | 7168 | 0% | |
Number of bonded IOBs | 5 | 141 | 3% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | دنشلبم 13. كارس 16:44:18 2017 | ||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Synthesis Simulation Model Report | Out of Date | دنشلبم 13. كارس 15:02:13 2017 | |
WebTalk Report | Current | سم شلبم 14. كارس 11:27:49 2017 | |
WebTalk Log File | Current | سم شلبم 14. كارس 11:27:54 2017 |