SDcard Project Status (05/06/2017 - 17:27:00)
Project File: SD_Secound.xise Parser Errors: No Errors
Module Name: SDcard Implementation State: Programming File Generated
Target Device: xc3s400-4pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
84 Warnings (15 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 177 7,168 2%  
Number of 4 input LUTs 397 7,168 5%  
Number of occupied Slices 245 3,584 6%  
    Number of Slices containing only related logic 245 245 100%  
    Number of Slices containing unrelated logic 0 245 0%  
Total Number of 4 input LUTs 452 7,168 6%  
    Number used as logic 397      
    Number used as a route-thru 55      
Number of bonded IOBs 12 141 8%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.54      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentمارشلبم 10. كم 15:18:29 2017081 Warnings (15 new)2 Infos (0 new)
Translation ReportCurrentمارشلبم 10. كم 15:18:35 2017000
Map ReportCurrentمارشلبم 10. كم 15:18:40 2017003 Infos (0 new)
Place and Route ReportCurrentمارشلبم 10. كم 15:18:49 201703 Warnings (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentمارشلبم 10. كم 15:18:53 2017006 Infos (0 new)
Bitgen ReportCurrentمارشلبم 10. كم 15:18:59 2017001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Dateمارشلبم 10. كم 15:18:59 2017
WebTalk Log FileOut of Dateمارشلبم 10. كم 15:19:04 2017

Date Generated: 05/14/2017 - 16:21:26