Counter Project Status (04/07/2017 - 01:59:53) | |||
Project File: | Counter_verilog.xise | Parser Errors: | X 1 Error |
Module Name: | Counter | Implementation State: | Synthesized (Failed) |
Target Device: | xc3s400-5pq208 |
|
|
Product Version: | ISE 14.7 |
|
|
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 1 | 3584 | 0% | |
Number of 4 input LUTs | 1 | 7168 | 0% | |
Number of bonded IOBs | 4 | 141 | 2% | |
Number of GCLKs | 1 | 8 | 12% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | جمعه 7. آوريل 01:48:02 2017 | ||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |