Counter_VHDL Project Status (04/07/2017 - 02:08:02)
Project File: Counter_verilog.xise Parser Errors: No Errors
Module Name: Counter_VHDL Implementation State: Synthesized
Target Device: xc3s400-5pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 1 3584 0%
Number of 4 input LUTs 1 7168 0%
Number of bonded IOBs 4 141 2%
Number of GCLKs 1 8 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentجمعه 7. آوريل 02:08:01 2017000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 04/07/2017 - 02:08:02