Counter_VHDL Project Status (04/07/2017 - 02:08:02) | |||
Project File: | Counter_verilog.xise | Parser Errors: | No Errors |
Module Name: | Counter_VHDL | Implementation State: | Synthesized |
Target Device: | xc3s400-5pq208 |
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No Errors |
Product Version: | ISE 14.7 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 1 | 3584 | 0% | |
Number of 4 input LUTs | 1 | 7168 | 0% | |
Number of bonded IOBs | 4 | 141 | 2% | |
Number of GCLKs | 1 | 8 | 12% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | جمعه 7. آوريل 02:08:01 2017 | 0 | 0 | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |