SPI Project Status (04/28/2017 - 19:25:51)
Project File: SPI_FPGA.xise Parser Errors: No Errors
Module Name: SPI Implementation State: Programming File Not Generated
Target Device: xc3s400-4pq208
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentجمعه 28. آوريل 19:25:43 2017
WebTalk Log FileCurrentجمعه 28. آوريل 19:25:51 2017

Date Generated: 04/28/2017 - 19:25:51