SPI_slave Project Status (04/29/2017 - 14:47:02)
Project File: SPI_FPGA.xise Parser Errors: No Errors
Module Name: SPI_slave Implementation State: Synthesized
Target Device: xc3s400-4pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
11 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 14 3584 0%
Number of Slice Flip Flops 22 7168 0%
Number of 4 input LUTs 17 7168 0%
Number of bonded IOBs 9 141 6%
Number of GCLKs 1 8 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentشنبه 29. آوريل 17:36:52 2017011 Warnings (0 new)0
Translation ReportOut of Dateشنبه 29. آوريل 17:30:33 2017000
Map ReportOut of Dateشنبه 29. آوريل 17:30:38 2017002 Infos (0 new)
Place and Route ReportOut of Dateشنبه 29. آوريل 17:30:45 2017002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportOut of Dateشنبه 29. آوريل 17:30:48 2017006 Infos (0 new)
Bitgen ReportOut of Dateشنبه 29. آوريل 17:30:54 2017001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Dateشنبه 29. آوريل 17:30:54 2017
WebTalk Log FileOut of Dateشنبه 29. آوريل 17:30:59 2017

Date Generated: 04/29/2017 - 17:37:37