SPI_slave Project Status (04/29/2017 - 14:47:02) | |||
Project File: | SPI_FPGA.xise | Parser Errors: | No Errors |
Module Name: | SPI_slave | Implementation State: | Synthesized |
Target Device: | xc3s400-4pq208 |
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No Errors |
Product Version: | ISE 14.7 |
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11 Warnings (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 14 | 3584 | 0% | |
Number of Slice Flip Flops | 22 | 7168 | 0% | |
Number of 4 input LUTs | 17 | 7168 | 0% | |
Number of bonded IOBs | 9 | 141 | 6% | |
Number of GCLKs | 1 | 8 | 12% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | شنبه 29. آوريل 17:36:52 2017 | 0 | 11 Warnings (0 new) | 0 | |
Translation Report | Out of Date | شنبه 29. آوريل 17:30:33 2017 | 0 | 0 | 0 | |
Map Report | Out of Date | شنبه 29. آوريل 17:30:38 2017 | 0 | 0 | 2 Infos (0 new) | |
Place and Route Report | Out of Date | شنبه 29. آوريل 17:30:45 2017 | 0 | 0 | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | شنبه 29. آوريل 17:30:48 2017 | 0 | 0 | 6 Infos (0 new) | |
Bitgen Report | Out of Date | شنبه 29. آوريل 17:30:54 2017 | 0 | 0 | 1 Info (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | شنبه 29. آوريل 17:30:54 2017 | |
WebTalk Log File | Out of Date | شنبه 29. آوريل 17:30:59 2017 |